1. Field of the Invention
This invention relates generally to methods and structures for improving byte-oriented encoding, and more particularly to methods and structures that enable improvements in the reduction of encoded data run-length in high speed encoding.
2. Description of the Related Art
In the design and fabrication of DC-balanced, partitioned-block, high-speed, 8B/10B encoders, it is well known that an encoded binary signal string with a long run-length, e.g., greater than five, destabilizes clock data recovery logic and produces unreliable clock data recovery in a high speed data communication application, such as a peripheral component interconnect express card. FIG. 1 shows a typical layout of a peripheral component interconnect express (PCIExpress) card 100 and illustrates how an 8B/10B encoder 106 may be used in conjunction with some other components on the PCIExpress card 100, such as a serializer 108 and a clock data recovery (CDR) unit 110. The PCIExpress card 100 is typically characterized by two blocks of circuitry; for example, a transmission block circuitry 102 and a reception block circuitry 104. The 8B/10B encoder 106 and the serializer 108 are considered to be transmission components and they are included in the transmission block circuitry 102. Whereas, the clock data recovery unit 110 is considered to be a reception component, and it is included in the reception block circuitry 104. A paper written by A. X. Windmer and P. A. Franaszek, A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code, describes a typical 8B/10B encoder and provides a discussion on eight-bit to ten-bit encoding logic. This paper and the discussion provided therefrom are incorporated herein by reference.
Typically, an encoder receives an input data string from an input line or data bus. The input data string comprises a string of bits identified, for example, by ABCDEFGH. To initiate encoding, the incoming bits of an input data string are partitioned into sub-strings, ABCDE and FGH, and classified. The five bits of classified sub-string ABCDE are encoded into six bits, abcdei, in accordance with 5B/6B encoding functions and disparity control, and the three bits of classified sub-string FGH are encoded into four bits, fghj, in accordance with 3B/4B encoding functions. Encoding tables are shown in FIGS. 2 and 3 illustrate typical 5B/6B and 3B/4B encoding functions, respectively, that are commonly performed in conventional encoders.
However, due to certain peculiarities in the coding functions of conventional encoders, they sometimes produce output data strings with a long run-length, e.g., greater than five. This destabilizes the clock data recovery logic and causes unreliable clock data recovery. A special character is used to execute bit encoding to avoid producing an output string with an undesirable run-length. However, in conventional encoders there is a delay in receiving the input signals that are used to determine the special character as a result of how such inputs are generated.
In low-speed applications, for example encoding processed at below 200 MHz, the delay from the conventional encoding logic circuitries have not caused any significant adverse effects on clock data recovery. However, for high-speed applications, for example, encoding processed at about 200 MHz and higher, the delay causes some encoding switches to select and process the wrong input. As a result, conventional encoders may produce output data strings having undesirable run-lengths, e.g., a run-length greater than five.
Accordingly, conventional encoders are not well suited for high-speed encoding. What is needed is an encoder that is capable of reliably and consistently producing output data strings with shorter run-lengths.